1. Field of the Invention
The present invention relates to an apparatus and related method for high efficiency and accuracy read caching of a south bridge, and more particularly, to an apparatus and related method for high efficiency and accuracy read caching of south bridge using north bridge address queuing.
2. Description of the Prior Art
A computer system is one of the most fundamental hardware devices in modern society. The way of making highly efficient and accurate computer systems is of key importance.
A typical computer system comprises a central processing unit, a chip set that includes a south bridge and a north bridge, system memory, and peripheral devices. The central processing unit controls the operation of data processing and computation; the system memory stores data needed by the central processing unit during the operation. The north bridge is electrically connected to the central processing unit and the system memory. The south bridge is electrically connected to the peripheral devices via a bus, such as a PCI bus; the chip set coordinates the data exchange between the central processing unit, the system memory and the peripheral devices. For example, when a peripheral device, such as a hard drive or a CD-ROM, reads data of specified addresses from the system memory, the peripheral device sends a request to the south bridge for data reading, and then the south bridge coordinates the north bridge to read the data of the specified addresses from the system memory and transmits the data to the peripheral device via the south bridge, so thus, the request of the peripheral device is fulfilled.
In order to improve the efficiency of the peripheral devices, the south bridge can perform read caching. When a peripheral device is reading data of specified addresses from the system memory, the south bridge not only informs the north bridge for reading data of the specified addresses, but also requests that the north bridge read extra data at the adjoining addresses as pre-fetched read data. After the north bridge completes data reading, the south bridge transmits the data of the specified addresses to the peripheral device to fulfill its request, and the pre-fetched read data then is stored in the south bridge. Next time, as the peripheral device requests data of other addresses from the system memory, the south bridge checks if the addresses of the pre-fetched read data match the addresses of the requested data, and if so, the south bridge transmits the pre-fetched read data to the peripheral device without going through the north bridge for reading data in the system memory. Therefore, the south bridge can fulfill the peripheral device's request faster.
For example, when the peripheral device is performing a burst read of the system memory, the peripheral device asks for data of four sequential addresses AD(n), AD(n+1), AD(n+2) and AD(n+3). When performing read caching, the south bridge requests that the north bridge read eight data of sequential addresses AD(n) to AD(n+7) from the system memory, wherein, the data of addresses AD(n) to AD(n+3) is requested by the peripheral device, and the south bridge transmits these four data to the peripheral device. Then the rest of the four data are stored in the south bridge as the pre-fetched read data. Next time, when the peripheral device asks for data, if the data of addresses AD(n+4) to AD(n+7) is what the peripheral device needs, the south bridge transmits these pre-fetched read data to the peripheral device directly. Because one of the peripheral device's characteristics is regularly reading data of adjoining addresses from the system memory, read caching of the south bridge can improve the efficiency of the peripheral device.
On the other hand, as known by those skilled in the art, the central processing unit of the computer system also has an internal cache (cache memory). The central processing unit reads the data from the system memory via the north bridge and stores it into the cache, and then uses the cache to store and read the data during operation. When the central processing unit is executing a program, it may use one of the system memory's data spaces, for example address AD(m), for temporarily storing a parameter; the central processing unit reads the data of address AD(m) from the system memory via the north bridge, and stores it into the cache. Then, following the procedure of the program, supposing that the data of the address AD(m) should be updated, the central processing unit can directly update the data in the cache without writing back to the system memory. Of course, the central processing unit will write back the data to the system memory at some specific time, but the potential of the cache would be wasted if the central processing unit wrote back to the system memory frequently.
Both the read caching of the south bridge and the cache of the central processing unit are designed for improving the efficiency of the computer system, however, data incoherence may result if these two mechanisms work at the same time. For example, when the data of address AD(m) is stored in the south bridge as a pre-fetched read data and also read into the cache of the central processing unit, at this moment, if the central processing unit updates the data of address AD(m), the south bridge cannot detect that the data has being updated, and thus the data in the south bridge is out of date. Under such circumstance, if the south bridge transmits the data of address AD(m) to the peripheral device, it will cause data incoherence and make the computer system malfunction. This is because, with the data content of same address AD(m), the central processing unit already updates the data, but the peripheral device receives the non-updated data from the south bridge.
To avoid the above data incoherence, the prior art sets a counter in the south bridge for counting the lifetime of data. If the data storing time of the pre-fetched read data is over the default time or lifetime, the south bridge will be forced to invalidate the data. The assumption of this prior art is that as operation time of the computer system increases there is a higher possibility of each data in the system memory being read into the cache of the central processing unit; if data storing time of one certain address of data in the south bridge is over the default lifetime, the possibility of that certain address of data being read into the central processing unit is supposed to be over a critical value, which means it is possible that the certain address of data has been read into the cache of the central processing unit. In order to prevent data incoherence, the south bridge should not keep the original data contents of this certain address of data, but invalidate it.
In other words, in the above prior art, the south bridge cannot detect whether the pre-fetched read data is updated in the cache of the central processing unit, and thus cannot actually prevent data incoherence. Moreover, if the lifetime is set too short, the south bridge must invalidate the pre-fetched read data frequently; under this circumstance, the south bridge may invalidate pre-fetched read data, which has not been read into the cache of the central processing unit, without using these pre-fetched read data efficiently. In addition, each invalidation will affect the efficiency of the operation of the south and north bridges. On the other hand, if the lifetime is too long, data incoherence is more common.